Conference paper
A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
A -3.3-V half-rate clock 4:1 multiplexer implemented in a 210-GHz f T 0.13-μm SiGe-bipolar technology and operating up to 132 Gb/s is reported. Among many design challenges, the control of on-chop clock distribution was critical to achieve such a high data rate. At 100 Gb/s, the chip operates reliably down to -3.0-V supply voltage and up to 100°C chip temperature. The circuit consumes 1.45 W from a -3.3-V supply voltage and exhibits less than 340-fs rms jitter on the output data.
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
Mounir Meghelli
BCTM 2004
Gautam R. Gangasani, Chun-Ming Hsu, et al.
IEEE JSSC
Mounir Meghelli
CSICS 2004