A low power adaptive clock and data recovery circuit for wireless implantable systems

An extremely low power clock and data recovery circuit was designed for pulse position modulated input. Synchronized clock and data were recovered through converting the timing distance between pulses into voltage domain. The reference voltage required for data recovery was adaptively generated to extend the range of the input data rate. The design was validated using 0.25 μm CMOS technology. With 45.5 kbits/s input data, the entire circuit only consumes less than 13 μW of power.