Phillip J. Restle, Timothy G. McNamara, et al.
IEEE Journal of Solid-State Circuits
The variability of CMOS device propagation delay is measured with a special test circuit. The circuit detects AC delay variations, as distinct from the DC effect of threshold voltage variation. The AC variability is likely due to the vertical resistance of the gate-stack. A comparison of two technologies, using gate-first and gate-last gate-stacks, shows much reduced variability of the gate-last FETs. This is attributed to the absence of interfacial dopant fluctuation and the presence of tailored metallic interfaces in gate-last technologies.
Phillip J. Restle, Timothy G. McNamara, et al.
IEEE Journal of Solid-State Circuits
Pouya Hashemi, Karthik Balakrishnan, et al.
VLSI Technology 2014
Shu-Jen Han, Satoshi Oida, et al.
IEEE Electron Device Letters
Joachim N. Burghartz, Mehmet Soyuer, et al.
IEEE Transactions on Electron Devices