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FPGA-based coprocessor for text string extraction
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The main interconnect of the massively parallel Blue Gene®/L is a three-dimensional torus network with dynamic virtual cut-through routing. This paper describes both the architecture and the microarchitecture of the torus and a network performance simulator. Both simulation results and hardware measurements are presented. © Copyright 2005 by International Business Machines Corporation.
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
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