Breakdown transients in ultrathin gate oxides: Transition in the degradation rate

The evolution of complementary metal-oxide-semiconductor (CMOS) devices in Si integrated circuits (IC) was driven so far by an aggressive device scaling associated with a slower decrease of the supply voltages. this resulted in an increase of the electric fields applied to the structures, with numerous positive consequences but some drawbacks. It was shown that this current was the main origin of the degradation leading to the dielectric breakdown (BD) of the gate dielectric nowadays an ultrathin SiO2 layer of 1-2 nm of thickness and with a large component of Si nitride at the Si/SiO2 interface.