Designing for a gigahertz

H. Peter Hofstee; Sang H. Dhong; David Meltzer; Kevin J. Nowka; Joel A. Silberman; Jeffrey L. Burns; Stephen D. Posluszny; Osamu Takahashi

doi:10.1109/40.683106

IEEE Micro

Paper

01 May 1998

Designing for a gigahertz

View publication

Abstract

Using a circuit-centric approach, a small team constructed a gigahertz integer processor, more than doubling the frequency of full-fledged designs in the same technology.

Paper

A 14-ns 4-Mb CMOS DRAM with 300-mW Active Power

Toshiaki Kirihata, Sang H. Dhong, et al.

IEEE Journal of Solid-State Circuits

Paper

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Brian Flachs, Shigehiro Asano, et al.

IBM J. Res. Dev

Paper

ExtraV: Boosting graph processing near storage with a coherent accelerator

Jinho Lee, Heesu Kim, et al.

VLDB

Paper

1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro

Osamu Takahashi, Sang H. Dhong, et al.

IEEE Journal of Solid-State Circuits

View all publications

Abstract

Related

A 14-ns 4-Mb CMOS DRAM with 300-mW Active Power

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

ExtraV: Boosting graph processing near storage with a coherent accelerator

1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro