J.C. Marinace
JES
The design and packaging of integrated circuits requires the calculation of capacitances for three-dimensional conductors located on parallel planes. An integral-equation (IE) computer-solution technique is presented, which provides accurate results. The solution technique minimizes computer storage requirements while maintaining calculating efficiency without excessive computation times. Copyright © 1973 by The Institute of Electrical and Electronics Engineers, Inc.
J.C. Marinace
JES
S. Cohen, T.O. Sedgwick, et al.
MRS Proceedings 1983
Peter J. Price
Surface Science
E. Burstein
Ferroelectrics