Conference paper
Stable SRAM cell design for the 32 nm node and beyond
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VLSI Technology 2005
The early conceptual stages and key elements in the development of the one-device MOSFET dynamic RAM are reviewed from the personal perspective of the author. Future miniaturization to the level of 1/4μm channel length and minimum lithography dimension is projected. © 1984 IEEE
Leland Chang, David M. Fried, et al.
VLSI Technology 2005
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