HARP: Heterogeneous Analog-Digital Resource-aware Performance and Scheduling Framework for Transformer Acceleration

As deep learning models grow in size and complexity, data movement, rather than raw compute, has become the dominant performance bottleneck. Analog Compute-In-Memory (ACIM) mitigates this by performing multiply-accumulate operations directly in memory, eliminating repeated weight transfers and achieving order-of-magnitude energy efficiency gains. However, their high weight write cost and lack of native support for non-linear operations require tight integration with digital units that support diverse execution modes such as vector-style and data-parallel processing. Despite growing interest, there is still lack of optimized tools to evaluate such heterogeneous ACIM-based systems at full-network scale. To address this, we present HARP, a unified framework for mapping and scheduling transformer workloads on heterogeneous systems combining ACIM units with digital accelerators supporting multiple execution flows. HARP explores latency-, area-, and balanced mapping strategies for ACIM, exploiting crossbars weight reuse to preserve efficiency, and constructs hybrid schedules that exploit both inter- and intra-layer parallelism through fine-grained pipelining, overlapping execution across analog and digital units while respecting each unit’s dataflow constraints. By accepting arbitrary architectural parameters, HARP serves as both a fast and accurate performance estimator and a tool for rapid design-space exploration or hardware-aware neural architecture search. Evaluated on transformers, HARP reduces end-to-end latency by up to 14.54 × over a non-pipelined baseline and 7.59 × over a single-vector pipeline adopted in state-of-the-art ACIM simulators. HARP will be open-sourced upon the paper’s acceptance.