Raymond Wu, Jie Lu
ITA Conference 2007
Victor V256 is a partitionable message-passing multiprocessor with 256 processors, designed and in use at the IBM Thomas J. Watson Research Center. Our goals are to explore computer architectures based on the message-passing model and to use these architectures to solve real applications. We present the architecture of the Victor system, particularly its partitioning and nonintrusive monitoring. We discuss some of the programming environments on Victor, such as E-kernel, an embedding kernel developed for the support of program mapping and network reconfiguration. We review applications developed and run on Victor and discuss a few in depth, concluding with insights we have gained from this project.
Raymond Wu, Jie Lu
ITA Conference 2007
Kaoutar El Maghraoui, Gokul Kandiraju, et al.
WOSP/SIPEW 2010
Fan Jing Meng, Ying Huang, et al.
ICEBE 2007
Michael D. Moffitt
ICCAD 2009