Limits to Jitter in Digital CMOS Gates

The time delay of digital signals propagating through CMOS gates is unavoidably subject to some timing jitter, which imposes a lower limit on circuit jitter performance. Some of the jitter is fundamental to the nature of CMOS gates, and cannot be eliminated, and some is due to power supply noise, which can be controlled to some extent. A technique for distinguishing between these two components, and obtaining their numerical values, is described, and the technique is demonstrated with simple inverters.