Conference paper
Process-variation-tolerant zero skew clock routing
Shen Lin, C.K. Wong
Annual ASIC Conference and Exhibit 1993
The problem considered here is that of permuting the pins of modules in order to maximize the number of connections which can be achieved in the polysilicon level. Using a graph-theoretic formulation, the problem is shown to be equivalent to that of removing fewest edges in a certain graph to break all cycles. The problem is proved to be NP-complete. A heuristic based on branch-and-bound is proposed. © 1984.
Shen Lin, C.K. Wong
Annual ASIC Conference and Exhibit 1993
W.D. Frazer, C.K. Wong
CACM
Ashok K. Chandra, C.K. Wong
IEEE TC
P. Widmayer, L. Woo, et al.
Integration, the VLSI Journal