Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops

Keith A. Jenkins; James P. Eckhardt

doi:10.1109/54.844337

IEEE Design and Test of Computers

Paper

01 Apr 2000

Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops

View publication

Abstract

Excessive "jitter," caused primarily by power supply noise, can detract from the advantages of phase-locked loops. Moreover, in a multichip system, the accumulated phase error must be measured - not just the jitter.

Paper

Understanding and Measuring the Jitter Generated by Digital CMOS Gates

Keith A. Jenkins

CSSP

Conference paper

Statistical characterization and on-chip measurement methods for local random variability of a process using sense-amplifier-based test structure

Saibal Mukhopadhyay, Keunwoo Kim, et al.

ISSCC 2007

Paper

Identification of gate electrode discontinuities in submicron CMOS technologies, and effect on circuit performance

Keith A. Jenkins, Joachim N. Burghartz, et al.

IEEE Transactions on Electron Devices

Paper

Multifinger embedded T-shaped gate graphene RF transistors with high ratio

Shu-Jen Han, Satoshi Oida, et al.

IEEE Electron Device Letters

View all publications

Abstract

Related

Understanding and Measuring the Jitter Generated by Digital CMOS Gates

Statistical characterization and on-chip measurement methods for local random variability of a process using sense-amplifier-based test structure

Identification of gate electrode discontinuities in submicron CMOS technologies, and effect on circuit performance

Multifinger embedded T-shaped gate graphene RF transistors with high ratio