Conference paper
COUNTERFACTUAL CONCEPT BOTTLENECK MODELS
Gabriele Dominici, Pietro Barbiero, et al.
ICLR 2025
We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components. © 2006 Elsevier B.V. All rights reserved.
Gabriele Dominici, Pietro Barbiero, et al.
ICLR 2025
Thomas M. Cheng
IT Professional
Bowen Zhou, Bing Xiang, et al.
SSST 2008
Pradip Bose
VTS 1998