Design considerations for 50G+ backplane linksThomas ToiflMatthias Braendliet al.2016ESSCIRC 2016Conference paper
A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-pathPier Andrea FranceseMatthias Braendliet al.2016ISSCC 2016Conference paper
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOSAlessandro CevreroCosimo Aprileet al.2015VLSI Circuits 2015Conference paper
Adaptive optical interconnects: The ADDAPT projectRonny HenkerJ. Plivaet al.2015SPIE Optics + Photonics 2015Conference paper