A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
- Gain Kim
- Marcel Kossel
- et al.
- 2020
- IEEE JSSC
Paper
Publications
8 results for Andreas Burg
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET
- Gain Kim
- Lukas Kull
- et al.
- 2019
- A-SSCC 2019
Conference paper30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
- Gain Kim
- Lukas Kull
- et al.
- 2019
- ISSCC 2019
Conference paperDesign Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2018
- IEEE TCAS-I
PaperDesign considerations on sliding-block viterbi detectors for high-speed data transmission
- Hazar Yueksel
- Giovanni Cherubini
- et al.
- 2016
- ICSPCS 2016
Conference paperHigh-speed link with trellis-coded modulation and Reed-Solomon coding
- Hazar Yueksel
- Giovanni Cherubini
- et al.
- 2016
- CSCN 2016
Conference paperA 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Conference paperA 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- Hazar Yueksel
- Lukas Kull
- et al.
- 2015
- ESSCIRC 2015
Conference paper