Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters
- Toke M. Andersen
- Florian Krismer
- et al.
- 2017
- IEEE-TEPL
Paper
Publications
95 results for Thomas Toifl
Design considerations on sliding-block viterbi detectors for high-speed data transmission
- Hazar Yueksel
- Giovanni Cherubini
- et al.
- 2016
- ICSPCS 2016
Conference paperHigh-speed link with trellis-coded modulation and Reed-Solomon coding
- Hazar Yueksel
- Giovanni Cherubini
- et al.
- 2016
- CSCN 2016
Conference paperExploration of inductor-based hybrid integrated voltage regulator architectures
- Arvind Sridhar
- Thomas Brunschwiler
- et al.
- 2016
- ESTC 2016
Conference paperCMOS ADCs Towards 100 GS/s and beyond
- Lukas Kull
- Danny Luu
- et al.
- 2016
- CSICS 2016
Conference paperFeedback delay reduction of Tomlinson- Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic
- Marcel Kossel
- Matthias Braendli
- et al.
- 2016
- Electronics Letters
PaperDesign considerations for 50G+ backplane links
- Thomas Toifl
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Conference paperA 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Conference paperImplementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
- Lukas Kull
- J. Pliva
- et al.
- 2016
- IEEE JSSC
PaperA 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
- 2016
- ISSCC 2016
Conference paper