Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology
- John U. Knickerbocker
- Chirag S. Patel
- et al.
- 2005
- CICC 2005
Conference paper
Publications
36 results for Chirag S. Patel
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
- John U. Knickerbocker
- Paul S. Andry
- et al.
- 2005
- IBM J. Res. Dev
PaperOptimal implementation of sea of leads (SoL) compliant interconnect technology
- Bing Dang
- Chirag Patel
- et al.
- 2004
- IITC 2004
Conference paperSea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)
- Muhannad S. Bakir
- Hollie A. Reed
- et al.
- 2003
- IEEE Transactions on Electron Devices
PaperElectrical test strategies for a wafer-level packaging technology
- David C. Keezer
- Chirag S. Patel
- et al.
- 2003
- IEEE Transactions on Electronics Packaging Manufacturing
PaperInterconnect opportunities for gigascale integration
- James D. Meindl
- Jeffrey A. Davis
- et al.
- 2002
- IBM J. Res. Dev
Review