Publications

2 results for T. Kawamura

Optimizing history effects in 65nm PD-SOI CMOS
- - Q. Liang
  - T. Kawamura
  - et al.
- 2006
- IEEE International SOI Conference 2006
Conference paper
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- - E. Leobandung
  - H. Nayakama
  - et al.
- 2005
- VLSI Technology 2005
Conference paper