Proposal of Package Structure Requirements for Effective Cooling from the Bottom Side of Chips (from the Substrate Side), Aiming for a Three-Dimensional (3D) Chip Stack
- Keiji Matsumoto
- Hiroyuki Mori
- 2016
- ECTC 2016
Conference paper
Publications
31 results for Keiji Matsumoto
Full intermetallic joints for chip stacking by using thermal gradient bonding
- T.L. Yang
- Toyohiro Aoki
- et al.
- 2016
- Acta Materialia
PaperThermal performance evaluation of dual-side cooling for a three-dimensional (3D) chip stack: Additional cooling from the laminate (substrate) side
- Keiji Matsumoto
- Hiroyuki Mori
- et al.
- 2016
- ICEP 2016
Conference paperAdvanced interconnect technologies in the era of cognitive computing
- Yasumitsu Orii
- Akihiro Horibe
- et al.
- 2016
- Pan Pacific 2016
Conference paperEmbedded power insert enabling dual-side cooling of microprocessors
- Thomas Brunschwiler
- Dominic Gschwend
- et al.
- 2015
- ECTC 2015
Conference paperDual-side cooling for a three-dimensional (3D) chip stack : Additional cooling from the laminate (substrate) side
- Keiji Matsumoto
- Hiroyuki Mori
- et al.
- 2015
- ECTC 2015
Conference paperCooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack
- Keiji Matsumoto
- Hiroyuki Mori
- et al.
- 2014
- 3DIC 2014
Conference paperPre-applied inter chip fill for 3D-IC joining
- Yasuhiro Kawase
- Makoto Ikemoto
- et al.
- 2014
- IMAPS 2014
Conference paperHigh thermal conductivity underfill for the thermal management of three-dimensional (3D) chip stacks
- Keiji Matsumoto
- Hiroyuki Mori
- et al.
- 2014
- SEMI-THERM 2014
Conference paperLaminate with thermal - Power insert for efficient front-side heat removal and power delivery
- Dominic Gschwend
- Timo Tick
- et al.
- 2014
- CIPS 2014
Conference paper