Publications

3 results for Charles C. Tanner

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- - John Barth
  - William R. Reohr
  - et al.
- 2008
- IEEE Journal of Solid-State Circuits
Paper
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- - John Barth
  - William Reohr
  - et al.
- 2007
- ISSCC 2007
Conference paper
A 0.127 μm² high performance 65 nm SOI based embedded DRAM for on-processor applications
- - G. Wang
  - K. Cheng
  - et al.
- 2006
- IEDM 2006
Conference paper