Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
Conference paper
Publications
8 results for W. Wang
Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures
- Nicolas Breil
- A. Carr
- et al.
- 2017
- VLSI Technology 2017
Conference paperA universal hardware-driven PVT and layout-aware predictive failure analytics for SRAM
- Rajiv V. Joshi
- Sudesh Saroop
- et al.
- 2016
- IEEE Transactions on VLSI Systems
PaperTransistor Matching and Fin Angle Variation in FinFET Technology
- Samarth Agarwal
- Terence B. Hook
- et al.
- 2015
- IEEE T-ED
PaperHigh performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Conference paperReplacement metal gate resistance in FinFET architecture modelling, validation and extendibility
- Ruqiang Bao
- Brian Greene
- et al.
- 2015
- IEDM 2015
Conference paperIntelligent bipolar control of MEMS capacitive switches
- Guanghai Ding
- David Molinero
- et al.
- 2013
- IEEE T-MTT
PaperAnalysis of electron mobility in inversion-mode Al2O 3InxGa1-xAs MOSFETs
- Weike Wang
- James C. M. Hwang
- et al.
- 2011
- IEEE T-ED
Paper