Voltage ramp stress based stress-and-sense test method for reliability characterization of Hf-base high-k/metal gate stacks for CMOS technologies
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- ECS Meeting 2011
Conference paper
Publications
31 results for Siddarth A. Krishnan
Voltage ramp stress for bias temperature instability testing of metal-gate/high- k stacks
- Andreas Kerber
- Siddarth A. Krishnan
- et al.
- 2009
- IEEE Electron Device Letters
PaperScaling deep trench based eDRAM on SOI to 32nm and beyond
- G. Wang
- D. Anand
- et al.
- 2009
- IEDM 2009
Conference paperThe effect of interface thickness of high-k/metal gate stacks on NFET dielectric reliability
- Barry P. Linder
- Eduard Cartier
- et al.
- 2009
- IRPS 2009
Conference paperTDDB failure distribution of metal gate / high-k CMOS devices on SOI substrates
- A. Kerber
- E. Cartier
- et al.
- 2009
- IRPS 2009
Conference paperA new methodology for characterizing the progressive BD of HfO 2/SiO2 metal gate stacks
- R. Pagano
- S. Lombardo
- et al.
- 2008
- SBMicro 2008
Conference paperGate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- K. Henson
- H. Bu
- et al.
- 2008
- IEDM 2008
Conference paperA novel approach to characterization of progressive breakdown in high-k/metal gate stacks
- R. Pagano
- S. Lombardo
- et al.
- 2008
- Microelectronics Reliability
PaperMobility and charge trapping comparison for crystalline and amorphous HfON and HfSiON gate dielectrics
- P.D. Kirsch
- M.A. Quevedo-Lopez
- et al.
- 2006
- Applied Physics Letters
PaperHigh performance gate first HfSiON dielectric satisfying 45nm node requirements
- M.A. Quevedo-Lopez
- S. Krishnan
- et al.
- 2005
- IEDM 2005
Conference paper