Technology impacts on sub-90nm CMOS circuit design & design methodologies
- Ruchir Puri
- Tanay Karnik
- et al.
- 2006
- VLSID 2006
Conference paper
Publications
216 results for Rajiv V. Joshi
Assembly technology for three dimensional integrated circuits
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- VMIC 2005
Conference paperCarbon nanotube interconnects: Implications for performance, power dissipation and thermal management
- Navin Srivastava
- Rajiv V. Joshi
- et al.
- 2005
- IEDM 2005
Conference paperModeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2005
- ISQED 2005
Conference paperDirect temperature measurement for VLSI circuits and 3-D modeling of self-heating in sub-0.13 μm SOI technologies
- R.V. Joshi
- S.S. Kang
- et al.
- 2005
- VLSID 2005
Conference paperA novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI
- Rajiv V. Joshi
- Yuen Chan
- 2005
- ESSCIRC 2005
Conference paper3-D thermal modeling of FinFET
- R.V. Joshi
- José A. Pascual-Gutiérrez
- et al.
- 2005
- ESSDERC 2005
Conference paperA low-overhead virtual rail technique for SRAM leakage power reduction
- J.B. Kuang
- Hung Ngo
- et al.
- 2005
- ICCD 2005
Conference paperLeakage power analysis of 25-nm double-gate CMOS devices and circuits
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2005
- IEEE Transactions on Electron Devices
PaperVariability analysis for sub-100 nm PD/SOI CMOS SRAM cell
- Rajiv V. Joshi
- Saibal Mukhopadhyay
- et al.
- 2004
- ESSCIRC 2004
Conference paper