PD/SOI SRAM performance in presence of gate-to-body tunneling current
- Rajiv V. Joshi
- Ching-Te Chuang
- et al.
- 2003
- IEEE Transactions on VLSI Systems
Paper
Publications
216 results for Rajiv V. Joshi
Backend implications for thermal effects in 3d integrated soi structures
- D. Celo
- R.V. Joshi
- et al.
- 2003
- AMC 2003
Conference paperNew digital circuit techniques for total standby leakage reduction in nano-scale SOI technology
- Koushik K. Das
- Rajiv V. Joshi
- et al.
- 2003
- ESSCIRC 2003
Conference paperSimulation of the deposition of BCC metals including anistropic effects using 3D-films
- T. Smy
- R.V. Joshi
- 2003
- AMC 2003
Conference paperThree dimensional CMOS devices and integrated circuits
- Meikei Ieong
- Kathryn W. Guarini
- et al.
- 2003
- CICC 2003
Conference paperDesign and CAD Challenges in sub-90nm CMOS Technologies
- Kerry Bernstein
- Ching-Te Chuang
- et al.
- 2003
- ICCAD 2003
Conference paperFinFET Technology for Future Microprocessors
- T. Ludwig
- I. Aller
- et al.
- 2003
- IEEE International SOI Conference 2003
Conference paperA New Dynamic Beta-Ratio Circuit Technique for Strained-Si Technology
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2003
- IEEE International SOI Conference 2003
Conference paperOxide breakdown model and its impact on SRAM cell functionality
- R. Rodríguez
- R.V. Joshi
- et al.
- 2003
- SISPAD 2003
Conference paperInfluence and model of gate oxide breakdown on CMOS inverters
- R. Rodríguez
- J.H. Stathis
- et al.
- 2003
- Microelectronics Reliability
Conference paper