A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET
- Jaewon Lee
- Pier-Andrea Francese
- et al.
- 2025
- IEEE Journal of Solid State Circuits
Paper
Publications
6 results for Yujin Choi
A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2025
- IEEE Transactions on Very Large Scale Integration VLSI Systems
PaperA DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
PaperA Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
PaperA Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers
- Donggeon Kim
- Yujin Choi
- et al.
- 2024
- IEEE TCAS-I
PaperRecent Advances in Ultra-High-Speed Wireline Receivers with ADC-DSP-Based Equalizers
- Seoyoung Jang
- Jaewon Lee
- et al.
- 2024
- IEEE Open Journal of the Solid-State Circuits Society
Paper