Gate oxide breakdown under Current Limited Constant Voltage Stress
- B.P. Linder
- J.H. Stathis
- et al.
- 2000
- Digest of Technical Papers-Symposium on VLSI Technology
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Publications
62 results for A. Ray
High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
- M. Hargrove
- S.W. Crowder
- et al.
- 1998
- IEDM 1998
Conference paperTrade-offs in the integration of high performance devices with trench capacitor DRAM
- S.W. Crowder
- S. Stiffler
- et al.
- 1997
- IEDM 1997
Conference paperA High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology
- S. Subbanna
- P. Agnello
- et al.
- 1996
- IEDM 1996
Conference paperHigh-performance 0.08 μm CMOS
- L. Su
- S. Subbanna
- et al.
- 1996
- VLSI Technology 1996
Conference paperA 0.5 μm fully scaled two-level metal fully planarized interconnect structure fabricated with X-ray lithography
- D. Moy
- L.K. Wang
- et al.
- 1990
- VLSI Technology 1990
Conference paperTwo-level metal fully planarized interconnect structure implemented on a 64 kb CMOS SRAM
- D. Moy
- M. Schadt
- et al.
- 1989
- VMIC 1989
Conference paperNITRIDED SiO//2 FILMS FOR VLSI APPLICATIONS.
- A. Ray
- C.J. Merz
- et al.
- 1984
- ECS Meeting 1984
Conference paperNITRIDED SiO//2 FILMS FOR VLSI APPLICATIONS.
- A. Ray
- C.J. Merz
- et al.
- 1984
- ECS Meeting 1984
Conference paperNitridation of silicon in a multiwafer plasma system
- A. Reisman
- M. Berkenblit
- et al.
- 1984
- Journal of Electronic Materials
Paper