Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Conference paper
Publications
7 results for J. Zhang
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
Conference paperScaling opportunities for Gate-All-Around and beyond: A patterning perspective
- Indira Seshadri
- Eric Miller
- et al.
- 2023
- IEDM 2023
Invited talkHighly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Subhadeep Kal
- et al.
- 2021
- ECS Meeting 2021
Conference paperEnabling Next Generation CMOS by Novel EOT Scaling Module
- Lin Dong
- Steven Hung
- et al.
- 2021
- VLSI Technology 2021
Conference paperStructural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices
- Shogo Mochizuki
- B. Colombeau
- et al.
- 2020
- VLSI Technology 2020
Conference paperDirected self-assembly of block copolymers for 7 nanometre FinFET technology and beyond
- Charlie Liu
- Elliott Franke
- et al.
- 2018
- Nature Electronics
Paper