NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paper
Publications
7 results for Albert Chu
Methodology Development to Benchmark Power Delivery Designs in Advanced Technology Nodes
- Nicholas A. Lanzillo
- A. Chu
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Conference paperPower Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes
- Nicholas A. Lanzillo
- Albert Chu
- et al.
- 2021
- IEEE Transactions on VLSI Systems
PaperBenchmarking Power Delivery Network Designs at the 5-nm Technology Node
- Nicholas A. Lanzillo
- Albert M. Chu
- et al.
- 2021
- IEEE T-ED
PaperChallenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Conference paperRapid and Holistic Technology Evaluation for Exploratory DTCO in beyond 7nm Technologies
- Myung-Hee Na
- Albert Chu
- et al.
- 2018
- SISPAD 2018
Conference paperAccurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology
- Yoo-Mi Lee
- Myung-Hee Na
- et al.
- 2017
- IEDM 2017
Conference paper