Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability
- Aditya Bansal
- Rahul Rao
- et al.
- 2009
- Microelectronics Reliability
Paper
Publications
46 results for Jae-Joon Kim
A 32 kb 10T sub-threshold sram array with bit-interleaving and differential read scheme in 90 nm CMOS
- Ik Joon Chang
- Jae-Joon Kim
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
PaperRing oscillator circuit structures for measurement of isolated NBTI/PBTI effects
- Jae-Joon Kim
- Rahul Rao
- et al.
- 2008
- ICICDT 2008
Conference paperCapacitive coupling based transient negative bit-line voltage (tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies
- S. Mukhopadhyay
- R.M. Rao
- et al.
- 2008
- ISCAS 2008
Conference paperDesign and analysis of a self-repairing SRAM with on-chip monitor and compensation circuitry
- Niladri Narayan Mojumder
- Saibal Mukhopadhyay
- et al.
- 2008
- VTS 2008
Conference paperOptimal dual-VT design in sub-100 nanometer PDSOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- VLSID 2008
Conference paperOn-chip process variation detection using slew-rate monitoring circuit
- Amlan Ghosh
- Rahul M. Rao
- et al.
- 2008
- VLSID 2008
Conference paperOptimal dual-VT design in sub-100-nm PD/SOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
PaperA 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS
- Ik Joon Chang
- Jae-Joon Kim
- et al.
- 2008
- ISSCC 2008
Conference paperCompletely digital on-chip circuit for local-random-variability measurement
- Rahul Rao
- Keith A. Jenkins
- et al.
- 2008
- ISSCC 2008
Conference paper