Hot Carrier Degradation and performance boost on Si Channel nFET Gate-All-Around Nanosheet Devices
- H. Zhou
- M. Hasanuzzaman
- et al.
- 2025
- IRPS 2025
Conference paper
Publications
10 results for R. Krishnan
Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Conference paperUV Assisted Densification of PerHydroPoIySilazane (PHPS) based Spin-On glass in High Aspect Ratio Gap Fill Structure
- S. Mehta
- H. Sheng
- et al.
- 2018
- ECS Meeting 2018
Conference paperModeling and characterization of gate leakage in high-K metal gate technology-Based embedded DRAM
- Mohit Bajaj
- Rajan K. Pandey
- et al.
- 2013
- IEEE T-ED
PaperCharacterization and optimization of charge trapping in high-k dielectrics
- Eduard Cartier
- Takashi Ando
- et al.
- 2013
- IRPS 2013
Conference paper22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Conference paperPerformance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- Balaji Jayaraman
- Sneha Gupta
- et al.
- 2012
- ICICDT 2012
Conference paperCharacterization of novel TiN/HfO2 metal insulator semiconductor stack for 32nm eDRAM
- Puneet Goyal
- Sneha Gupta
- et al.
- 2010
- IEEE International SOI Conference 2010
Conference paperA 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technology
- Nauman Z. Butt
- Kevin McStay
- et al.
- 2010
- IEDM 2010
Conference paperScaling deep trench based eDRAM on SOI to 32nm and beyond
- G. Wang
- D. Anand
- et al.
- 2009
- IEDM 2009
Conference paper