Full-wave PEEC time-domain method for the modeling of on-chip interconnects
- Phillip J. Restle
- Albert E. Ruehli
- et al.
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper
Publications
68 results for Phillip Restle
A clock distribution network for microprocessors
- Phillip J. Restle
- Timothy G. McNamara
- et al.
- 2001
- IEEE Journal of Solid-State Circuits
PaperOn-chip wiring design challenges for gigahertz operation operation
- Alina Deutsch
- Paul W. Coteus
- et al.
- 2001
- Proceedings of the IEEE
PaperClock tree and power grid design > 1 GHz
- Phillip J. Restle
- Albert Ruehli
- et al.
- 2000
- ADMETA 2000
Conference paperDealing with inductance in high-speed chip design
- P. Restle
- A.E. Ruehli
- et al.
- 1999
- DAC 1999
Conference paperDesigning the best clock distribution network
- P. Restle
- A. Deutsch
- 1998
- VLSI Circuits 1998
Conference paperMeasurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor
- P. Restle
- Keith A. Jenkins
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
PaperWhen are transmission-line effects important for on-chip interconnections?
- Alina Deutsch
- Gerard V. Kopcsay
- et al.
- 1997
- IEEE T-MTT
PaperImportance of inductance and inductive coupling for on-chip wiring
- A. Deutsch
- H. Smith
- et al.
- 1997
- IEEE Topical Meeting EPEPS 1997
Conference paperA 400-MHz S/390 microprocessor
- Charles F. Webb
- Carl J. Anderson
- et al.
- 1997
- IEEE Journal of Solid-State Circuits
Paper