Tolerating soft errors in processor cores using CLEAR (cross-layer exploration for architecting resilience)
- Eric Cheng
- Shahrzad Mirkhani
- et al.
- 2018
- IEEE TCADIS
Paper
Publications
3 results for Lukasz G. Szafaryn
CLEAR: Crosslayer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores
- Eric Cheng
- Shahrzad Mirkhani
- et al.
- 2016
- DAC 2016
Conference paperThe resilience wall: Cross-layer solution strategies
- Subhasish Mitra
- Pradip Bose
- et al.
- 2014
- VLSI-TSA 2014
Conference paper