Defect and grain boundary scattering in tungsten: A combined theoretical and experimental study
- Nicholas A. Lanzillo
- H. Dixit
- et al.
- 2018
- Journal of Applied Physics
Paper
Publications
9 results for Jin Cho
SiGe FinFET for practical logic libraries by mitigating local layout effect
- G. Tsutsui
- Huimei Zhou
- et al.
- 2017
- VLSI Technology 2017
Conference paper10nm FINFET technology for low power and high performance applications
- D. Guo
- H. Shang
- et al.
- 2014
- ICSICT 2014
Conference paperComprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- Abhijeet Paul
- Andres Bryant
- et al.
- 2013
- IEDM 2013
Conference paperFin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs
- Abhijeet Paul
- Chun-Chen Yeh
- et al.
- 2013
- S3S 2013
Conference paperSub-25nm FinFET with advanced fin formation and short channel effect engineering
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- VLSI Technology 2011
Conference paperOpportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- CSTIC 2011
Conference paperFinFET resistance mitigation through design and process optimization
- Cindy Wang
- Josephine Chang
- et al.
- 2009
- VLSI-TSA 2009
Conference paperOvercoming the challenges of 22-nm node patterning through litho-design co-optimization
- Martin Burkharde
- J.C. Arnold
- et al.
- 2009
- SPIE Advanced Lithography 2009
Conference paper