A low power and high performance SOI SRAM circuit design with improved cell stability
- R.V. Joshi
- Y. Chan
- et al.
- 2006
- IEEE SOI 2006
Conference paper
Publications
25 results for Y. Chan
Statistical exploration of the dual supply voltage space of a 65nm PD/SOI CMOS SRAM cell
- Rajiv Joshi
- Rouwaida Kanj
- et al.
- 2006
- ESSDERC 2006
Conference paperAn advanced optical diagnostic technique of IBM z990 eServer microprocessor
- Peilin Song
- Franco Stellari
- et al.
- 2005
- IEEE ITC 2005
Conference paperA novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI
- Rajiv V. Joshi
- Yuen Chan
- 2005
- ESSCIRC 2005
Conference paperVariability analysis for sub-100 nm PD/SOI CMOS SRAM cell
- Rajiv V. Joshi
- Saibal Mukhopadhyay
- et al.
- 2004
- ESSCIRC 2004
Conference paperA transregional CMOS SRAM with single, logic V DD and dynamic power rails
- Azeez J. Bhavnagarwala
- Stephen V. Kosonocky
- et al.
- 2004
- VLSI Circuits 2004
Conference paperHigh performance SRAMs in 1.5 V, 0.18μm partially depleted SOI technology
- R.V. Joshi
- A. Pellela
- et al.
- 2002
- VLSI Circuits 2002
Conference paperIBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology
- Brian W. Curran
- Yuen H. Chan
- et al.
- 2002
- IBM J. Res. Dev
PaperNon-invasive timing analysis of IBM G6 microprocessor L1 cache using backside time-resolved hot electron luminescence
- S. Polonsky
- D.R. Knebel
- et al.
- 2000
- ISSCC 2000
Conference paper2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 μm CMOS bulk technology
- R.V. Joshi
- S.P. Kowalczyk
- et al.
- 2000
- VLSI Circuits 2000
Conference paper