A 6+ Ghz 128Kb Multi-Port L1 Cache Using Ground Rule Clean 10T Bitcells in 5Nm Technology
- Rajiv Joshi
- John Davis
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paper
Publications
10 results for Gregory Fredeman
IBM z15: Physical design improvements to significantly increase content in the same technology
- Christopher Berry
- David Wolpert
- et al.
- 2020
- IBM J. Res. Dev
PaperIBM z15: A 12-Core 5.2GHz Microprocessor
- Christopher Berry
- Brian Bell
- et al.
- 2020
- ISSCC 2020
Conference paper4.1 22nm Next-generation IBM System z microprocessor
- J. Warnock
- Brian Curran
- et al.
- 2015
- ISSCC 2015
Conference paperA 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- John Barth
- Don Plass
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
PaperA 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
PaperA one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- Peter Klim
- John Barth
- et al.
- 2008
- VLSI Circuits 2008
Conference paperA 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
PaperA compact eFUSE programmable array memory for SOI CMOS
- John Safran
- Alan Leslie
- et al.
- 2007
- VLSI Circuits 2007
Conference paperA 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
Conference paper