A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
- Lukas Kull
- Danny Luu
- et al.
- 2017
- ISSCC 2017
Conference paper
Publications
21 results for Hazar Yueksel
Design considerations on sliding-block viterbi detectors for high-speed data transmission
- Hazar Yueksel
- Giovanni Cherubini
- et al.
- 2016
- ICSPCS 2016
Conference paperHigh-speed link with trellis-coded modulation and Reed-Solomon coding
- Hazar Yueksel
- Giovanni Cherubini
- et al.
- 2016
- CSCN 2016
Conference paperCMOS ADCs Towards 100 GS/s and beyond
- Lukas Kull
- Danny Luu
- et al.
- 2016
- CSICS 2016
Conference paperDesign considerations for 50G+ backplane links
- Thomas Toifl
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Conference paperA 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Conference paperA 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
- 2016
- ISSCC 2016
Conference paperA 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- Hazar Yueksel
- Lukas Kull
- et al.
- 2015
- ESSCIRC 2015
Conference paperA 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
- Alessandro Cevrero
- Cosimo Aprile
- et al.
- 2015
- VLSI Circuits 2015
Conference paperA 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS
- Pier Andrea Francese
- Thomas Toifl
- et al.
- 2014
- ESSCIRC 2014
Conference paper