SiGe FinFET for practical logic libraries by mitigating local layout effect
- G. Tsutsui
- Huimei Zhou
- et al.
- 2017
- VLSI Technology 2017
Conference paper
Publications
4 results for John R. Sporre
Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond
- Derren Dunn
- John R. Sporre
- et al.
- 2017
- SPIE Advanced Lithography 2017
Conference paperA 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Conference paperFINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
Conference paper