Publications

7 results for Alberto Cestero

SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology
- - Rajiv V. Joshi
  - J. Frougier
  - et al.
- 2025
- IEEE Open Journal of the Solid State Circuits Society
Paper
High Performance Nanosheet Technology Optimized for 77 K
- - R. Bao
  - L. Qin
  - et al.
- 2023
- IEDM 2023
Conference paper
3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS
- - J. Safran
  - Giri N. K. Rangan
  - et al.
- 2016
- ECTC 2016
Conference paper
A 0.039um² high performance eDRAM cell based on 32nm high-K/metal SOI technology
- - Nauman Z. Butt
  - Kevin McStay
  - et al.
- 2010
- IEDM 2010
Conference paper
Scaling deep trench based eDRAM on SOI to 32nm and beyond
- - G. Wang
  - D. Anand
  - et al.
- 2009
- IEDM 2009
Conference paper
A compact eFUSE programmable array memory for SOI CMOS
- - John Safran
  - Alan Leslie
  - et al.
- 2007
- VLSI Circuits 2007
Conference paper
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips
- - Norm Robson
  - John Safran
  - et al.
- 2007
- CICC 2007
Conference paper