A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
- Toshiaki Kirihata
- Martin Gall
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
Paper
Publications
34 results for Toshiaki Kirihata
220 mm2 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
- T. Kirihata
- M. Gall
- et al.
- 1998
- ISSCC 1998
Conference paperDevelopment of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
Conference paperFlexible test mode approach for 256-Mb DRAM
- Toshiaki Kirihata
- Hing Wong
- et al.
- 1997
- IEEE Journal of Solid-State Circuits
PaperFlexible test mode design for DRAM characterization
- H. Wong
- T. Kirihata
- et al.
- 1996
- VLSI Circuits 1996
Conference paperFault-tolerant designs for 256 Mb DRAM
- Toshiaki Kirihata
- Yohji Watanabe
- et al.
- 1996
- IEEE Journal of Solid-State Circuits
PaperA 286 mm2 256 Mb DRAM with ×32 both-ends DQ
- Yohji Watanabe
- Hing Wong
- et al.
- 1996
- IEICE Transactions on Electronics
PaperFault-tolerant designs for 256 Mb DRAM
- Toshiaki Kirihata
- Yohji Watanabe
- et al.
- 1996
- IEICE Transactions on Electronics
PaperA Variable Precharge Voltage Sensing
- Toshiaki Kirihata
- Sang H. Dhong
- et al.
- 1995
- IEEE Journal of Solid-State Circuits
PaperLow-noise TTL-compatible CMOS off-chip driver circuit
- S. Dhong
- M. Tanaka
- et al.
- 1995
- IBM J. Res. Dev
Paper