Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond
- Bruce Doris
- B. Desalvo
- et al.
- 2016
- Solid-State Electronics
Paper
Publications
7 results for Pierre Morin
Impact of source/drain silicon cap on FDSOI SiGe pMOSFET performance
- E. Augendre
- S. Maitrejean
- et al.
- 2015
- S3S 2015
Conference paperSilicon germanium FinFET device physics, process integration and modeling considerations (invited)
- Darsen Lu
- Pierre Morin
- et al.
- 2014
- ECSSMEQ 2014
Conference paperElastic relaxation in intrinsically-strained Fins: Simulations, physical and electrical characterization
- F. Allibert
- Pierre Morin
- et al.
- 2014
- S3S 2014
Conference paperDielectric isolated FinFETs on bulk substrate
- Darsen Lu
- Kangguo Cheng
- et al.
- 2014
- S3S 2014
Conference paperHigh performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
- Q. Liu
- M. Vinet
- et al.
- 2013
- IEDM 2013
Conference paperAggressively scaled strained silicon directly on insulator (SSDOI) FinFETs
- A. Khakifirooz
- R. Sreenivasan
- et al.
- 2013
- S3S 2013
Conference paper