CMOS and memories: From 100 nm to 10 nm!
- Sandip Tiwari
- Paul M. Solomon
- et al.
- 1999
- Microelectronic Engineering
Paper
Publications
167 results for Paul Solomon
Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
- H.-S. Wong
- David J. Franks
- et al.
- 1998
- IEDM 1998
Conference paperStraddle-gate transistor: Changing MOSFET channel length between off- and on-state towards achieving tunneling-defined limit of field-effect
- S. Tiwari
- J.J. Welser
- et al.
- 1998
- IEDM 1998
Conference paperBonding of thin films on 200 mm silicon wafers using chemical mechanical polishing
- E.C. Jones
- S. Tiwari
- et al.
- 1998
- IEEE International SOI Conference 1998
Conference paperSupply and threshold voltage optimization for low power design
- D.J. Frank
- P. Solomon
- et al.
- 1997
- LPED 1997
Conference paperThermodynamics of a charged fermion layer at high rs values
- S. Shapira
- U. Sivan
- et al.
- 1996
- Physical Review Letters
PaperThe thermodynamics of a charged fermion layer at high rs values
- S. Shapira
- U. Sivan
- et al.
- 1996
- Surface Science
PaperPower measurements of adiabatic circuits by thermoelectric technique
- P. Solomon
- D.J. Frank
- 1995
- LPE 1995
Conference paperElectroid-oriented adiabatic switching circuits
- D.J. Frank
- P. Solomon
- 1995
- ISLPED 1995
Conference paperSystem for direct measurement of the step response of electronic devices on the picosecond time scale
- J.A. Sheridan
- D.M. Bloom
- et al.
- 1995
- Optics Letters
Paper