Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Conference paper
Publications
26 results for X. Chen
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Conference paperA high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Conference paperReduced electromigration of Cu wires by surface coating
- C.-K. Hu
- L. Gignac
- et al.
- 2002
- Applied Physics Letters
PaperIntegration of copper and fluorosilicate glass for 0.18 μm interconnections
- E. Barth
- T. Ivers
- et al.
- 2000
- IITC 2000
Conference paper0.18 μm high-performance logic technology
- S.W. Crowder
- S. Greco
- et al.
- 1999
- VLSI Technology 1999
Conference paper