0.026μm2 high performance Embedded DRAM in 22nm technology for server and SOC applications
- C. Pei
- G. Wang
- et al.
- 2014
- IEDM 2014
Conference paper
Publications
7 results for J. Norum
22nm technology yield optimization using multivariate 3D virtual fabrication
- B. Cipriany
- B. Jagannathan
- et al.
- 2013
- SISPAD 2013
Conference paper22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Conference paperHigh performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Conference paperA 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
Conference paperA 0.168μm 2/0.11μm 2 highly scalable high performance embedded DRAM cell for 90/65-nm logic applications
- G. Wang
- P. Parries
- et al.
- 2005
- VLSI Technology 2005
Conference paperTrimming of hard-masks by gaseous chemical oxide removal (COR) for sub-10nm gates/fins, for gate length control and for embedded logic
- Wesley C. Natzle
- David Horak
- et al.
- 2004
- ASMC 2004
Conference paper