Access transistor design and optimization for 65/45nm high performance SOI eDRAM
- G. Wang
- P. Parries
- et al.
- 2008
- VLSI-TSA 2008
Conference paper
Publications
49 results for P. Agnello
(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
Conference paperCMOS fabricated by hybrid-orientation technology (HOT)
- Bin Yang
- M. Yang
- et al.
- 2007
- IEDST 2007
Conference paperOptimization of silicon technology for the IBM System z9
- Daniel J. Poindexter
- Scott R. Stiffler
- et al.
- 2007
- IBM J. Res. Dev
PaperHigh performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Conference paperHigh performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Conference paperDual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Conference paperHigh performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
Conference paperDual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Conference paperA high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Conference paper