High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Conference paper
Publications
10 results for B. Kim
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Conference paperCompetitive and cost effective copper/low-k interconnect (BEOL) for 28 nm CMOS technologies
- R. Augur
- C. Child
- et al.
- 2012
- Microelectronic Engineering
PaperCompetitive and cost effective copper/low-k interconnect (BEOL) for 28nm CMOS technologies
- Rod Augur
- Craig Child
- et al.
- 2010
- ADMETA 2010
Conference paperScaling deep trench based eDRAM on SOI to 32nm and beyond
- G. Wang
- D. Anand
- et al.
- 2009
- IEDM 2009
Conference paperStrained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy
- Yaocheng Liu
- Oleg Gluschenkov
- et al.
- 2007
- VLSI Technology 2007
Conference paper(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
Conference paperCMOS fabricated by hybrid-orientation technology (HOT)
- Bin Yang
- M. Yang
- et al.
- 2007
- IEDST 2007
Conference paperHigh performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Conference paperHigh performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Conference paper