A 6+ Ghz 128Kb Multi-Port L1 Cache Using Ground Rule Clean 10T Bitcells in 5Nm Technology
- Rajiv Joshi
- John Davis
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paper
Publications
8 results for Uma Srinivasan
24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology
- Alexander Fritsch
- Rajiv V. Joshi
- et al.
- 2021
- ISSCC 2021
Conference paperCase Study of Advanced Diagnostic Techniques for Multi Port Register File
- Uma Srinivasan
- William Huott
- et al.
- 2019
- NATW 2019
Conference paperA sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
- Azeez J. Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
PaperA sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2007
- VLSI Circuits 2007
Conference paperA low power and high performance SOI SRAM circuit design with improved cell stability
- R.V. Joshi
- Y. Chan
- et al.
- 2006
- IEEE SOI 2006
Conference paperAn advanced optical diagnostic technique of IBM z990 eServer microprocessor
- Peilin Song
- Franco Stellari
- et al.
- 2005
- IEEE ITC 2005
Conference paperA transregional CMOS SRAM with single, logic V DD and dynamic power rails
- Azeez J. Bhavnagarwala
- Stephen V. Kosonocky
- et al.
- 2004
- VLSI Circuits 2004
Conference paper