Gate movement for timing improvement on row based Dual-VDD designsHua XiangLakshmi Reddyet al.2016ISQED 2016Conference paper
Row based dual-vdd island generation and placementHua XiangHaifeng Qianet al.2014DAC 2014Conference paper
64-bit prefix adders: Power-efficient topologies and design solutionsChing ZhouBruce M. Fleischeret al.2009CICC 2009Conference paper