A 32 Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32 nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2014
- IEEE JSSC
Paper
Publications
8 results for Robert Reutemann
A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology
- Gautam R. Gangasani
- John F. Bulzacchelli
- et al.
- 2013
- A-SSCC 2013
Conference paperA 2.6 mW/Gbps 12.5 Gbps RX with 8-Tap switched-capacitor DFE in 32 nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
PaperA 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2011
- VLSI Circuits 2011
Conference paperA 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS
- Robert Reutemann
- Michael Ruegg
- et al.
- 2010
- IEEE Journal of Solid-State Circuits
PaperA 22-Gb/s PAM-4 receiver in 90-nm CMOS SOI technology
- Thomas Toifl
- Christian Menolfi
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
PaperA 0.94-ps-RMS-Jitter 0.016-mm 2 2.5-GHz Multiphase Generator PLL with 360° Digitally Programmable Phase Shift for 10-Gb/s Serial Links
- Thomas Toifl
- Christian Menolfi
- et al.
- 2005
- IEEE Journal of Solid-State Circuits
PaperA 22 Gbit/s PAM-4 receiver in 90nm CMOS-SOI technology
- Thomas Toifl
- Christian Menolfi
- et al.
- 2005
- VLSI Circuits 2005
Conference paper