Hole transport in nanoscale p-type MOSFET SOI devices with high strain
- H. Nayfeh
- S.-J. Jeng
- et al.
- 2007
- DRC 2007
Conference paper
Publications
28 results for Anthony Domenicucci
Implementation of robust nickel alloy salicide process for high-performance 65nm SOI CMOS manufacturing
- Jay Strane
- David Brown
- et al.
- 2007
- VLSI-TSA 2007
Conference paperHigh performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Conference paperHigh performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
Conference paperDevelopment of stacking faults in strained silicon layers
- S.W. Bedell
- A. Reznicek
- et al.
- 2005
- IEEE International SOI Conference 2005
Conference paperCharacterization of ultra thin SOI and SSOI substrates: Defect and strain analysis
- S.W. Bedell
- H.J. Hovel
- et al.
- 2005
- ECS Meeting 2005
Conference paperA hydrogen pre-bake process for Si epitaxy on sige surface
- H. Chen
- S.W. Bedell
- et al.
- 2004
- ECS Meeting 2004
Conference paperObservation of stacking faults in strained Si layers
- S.W. Bedell
- K.E. Fogel
- et al.
- 2004
- Applied Physics Letters
PaperQualification of 300 mm SOI CMOS substrate material: Readiness for development and manufacturing
- H.J. Hovel
- M. Almonte
- et al.
- 2004
- Solid-State Electronics
PaperQuick turnaround technique for highlighting defects in thin Si/SiGe bilayers
- S.W. Bedell
- D.K. Sadana
- et al.
- 2004
- Electrochemical and Solid-State Letters
Paper